A formal verification method of scheduling in high-level synthesis

Research output: Contribution to conference › Paper › peer-review

Original language	English
DOIs	https://doi.org/10.1109/ISQED.2006.10
Publication status	Published - Mar 2006
Externally published	Yes
Event	7th International Symposium on Quality Electronic Design - San Jose, USA Duration: 27 Mar 2006 → 29 Mar 2006

Conference	7th International Symposium on Quality Electronic Design
Period	27/03/06 → 29/03/06

Keywords

@conference{fa7c301c84d043279f9547e47dd52671,

title = "A formal verification method of scheduling in high-level synthesis",

keywords = "Formal methods, Computer science and informatics",

author = "C. Karfa and Chittaranjan Mandal and Dipankar Sarkar and Pentakota, \{Satyam R.\} and Chris Reade",

year = "2006",

month = mar,

doi = "10.1109/ISQED.2006.10",

language = "English",

note = "7th International Symposium on Quality Electronic Design ; Conference date: 27-03-2006 Through 29-03-2006",

}

TY - CONF

T1 - A formal verification method of scheduling in high-level synthesis

AU - Karfa, C.

AU - Mandal, Chittaranjan

AU - Sarkar, Dipankar

AU - Pentakota, Satyam R.

AU - Reade, Chris

PY - 2006/3

Y1 - 2006/3

KW - Formal methods

KW - Computer science and informatics

U2 - 10.1109/ISQED.2006.10

DO - 10.1109/ISQED.2006.10

M3 - Paper

T2 - 7th International Symposium on Quality Electronic Design

Y2 - 27 March 2006 through 29 March 2006

ER -