High-speed SMVs subscriber design for FPGA architectures

Modern power systems, particularly those integrating smart grid and microgrid functionalities, demand efficient high-speed data processing to manage increasingly complex operational requirements. In response to these challenges, this paper proposes a high-speed Sampled Measured Values (SMVs) subscriber design that leverages the programmability of Multi-Processor System-on-Chip (MPSoC) technology and the parallel processing capabilities of Field-Programmable Gate Arrays (FPGAs). By offloading SMVs data decoding to dedicated FPGA hardware, the approach significantly reduces processing latency and delivers deterministic performance, thereby surpassing traditional software-based implementations. This hardware acceleration is achieved without sacrificing flexibility, ensuring compatibility with emerging standards in IEC 61850 and offering scalability for expanding substation and grid communication networks. Experimental validations demonstrate lower end-to-end delays and improved throughput, highlighting the potential of the proposed system to meet stringent real-time requirements for monitoring and control in evolving smart grids.