Verification of scheduling in high-level synthesis

Research output: Contribution to conference › Paper › peer-review

Original language	English
DOIs	https://doi.org/10.1109/ISVLSI.2006.93
Publication status	Published - Mar 2006
Externally published	Yes
Event	IEEE Computer Society Annual Syposium on Emerging VLSI Technologies and Architectures 2006 - Karlsruhe, Germany Duration: 2 Mar 2006 → 3 Mar 2006

Conference	IEEE Computer Society Annual Syposium on Emerging VLSI Technologies and Architectures 2006
Period	2/03/06 → 3/03/06

Keywords

@conference{4722308e117843a8b81cb825d5e7bd8a,

title = "Verification of scheduling in high-level synthesis",

keywords = "Formal methods, Computer science and informatics",

author = "Chittaranjan Mandal and Dipankar Sarkar and S.R. Pentakota and Chris Reade and Chandan Karfa",

year = "2006",

month = mar,

doi = "10.1109/ISVLSI.2006.93",

language = "English",

note = "IEEE Computer Society Annual Syposium on Emerging VLSI Technologies and Architectures 2006 ; Conference date: 02-03-2006 Through 03-03-2006",

}

TY - CONF

T1 - Verification of scheduling in high-level synthesis

AU - Mandal, Chittaranjan

AU - Sarkar, Dipankar

AU - Pentakota, S.R.

AU - Reade, Chris

AU - Karfa, Chandan

PY - 2006/3

Y1 - 2006/3

KW - Formal methods

KW - Computer science and informatics

U2 - 10.1109/ISVLSI.2006.93

DO - 10.1109/ISVLSI.2006.93

M3 - Paper

T2 - IEEE Computer Society Annual Syposium on Emerging VLSI Technologies and Architectures 2006

Y2 - 2 March 2006 through 3 March 2006

ER -